Shallow trench isolation (“STI”) is a technique used for the isolation of neighboring transistors in a semiconductor device. It is particularly preferred in smaller isolation regions such as those experienced in sub-0.5 nm processing. Generally, shallow trenches are etched in the silicon and one or more dielectric materials are deposited in the trenches. Additional processing may be used to remove excess dielectric material, such as, for example, chemical-mechanical planarization.
In particular, multiple masking, ion implantation, annealing, plasma etching, and chemical and physical vapor deposition steps may be used in forming shallow trench structures in, for example, a shield gate semiconductor or other semiconductor gate structures.
More specifically, in an exemplary process for forming isolated areas on a semiconductor wafer involves growing a very thin silicon oxide layer on the order of 3 nm to 8 nm on a substrate of the wafer followed by depositing a layer of silicon nitride on the order of 100 nm to 250 nm, which is used as an oxide barrier. A patterned etch resistant resist layer is formed on the surface to define the areas where shallow trenches will not be formed and the shallow trenches are then etched into the substrate. The extent of etching proceeds even through under-etching of the silicon oxide layer into the silicon substrate defining wafer. The etched trenches are defined by sidewalls and a bottom.
An oxide liner is then applied across the surfaces (sidewalls and bottom) of the trench. The oxide liner does not substantially fill the trench. Rather, the oxide liner is applied to form a connected, continuous layer of silicon oxide across the wafer that is defined by the very thin silicon oxide layer applied to the wafer and the oxide liner applied across the surface of the trenches.
Optionally, the oxide liner may act as a sacrificial oxide for ion implantation into the sidewalls of the trench. Optionally, a nitride layer may be disposed across the oxide liner.
The remaining open space of the trench not occupied by the liner oxide is filled with a deposited oxide. Excess deposited oxide is removed with chemical mechanical planarization. Finally, the silicon nitride mask acting as the oxide barrier is removed.
Differences in STI geometries and variability in STI sizes can lead to vastly different charge buildup in the isolation oxide resulting in unexpected responses of the semiconductor gate response in operation. During the fabrication process, it is difficult to precisely control planarity and trench fill. For example, the trench oxide may become variably recessed below the active region of the gate oxide layer causing variations in peak electric fields that are experienced in the corner region of the trench.
Conventional processing techniques for controlling the gate to drain capacitance in a metal-oxide semiconductor using trench structures are notoriously limited resulting in a semiconductor having varying performance characteristics as a result of non-uniformity in passivation layer thicknesses and aspect ratios throughout the filled trench and other variations resulting from the fabrication processes.
There remains a need in the art for an improved system, process or method for filling the trenches of a semiconductor.